Zero-delay buffer circuit for a spread spectrum clock system and method therefor

ABSTRACT

A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a zero-buffer circuit for aspread spectrum clock (SSC) system and a method therefor and morespecifically, to a zero-delay buffer circuit having a delay-locked loop(DLL) based zero-delay buffer.

[0003] 2. Background of the Related Art

[0004] In a related art of improving computer system efficiency, it isdesirable to increase a processing speed by operating a centralprocessing unit (CPU) at a higher frequency by increasing a clockfrequency. An increase in clock frequency increases a frequency of thecomputer system, as peripherals (e.g., memory, graphic card) can alsooperate at a higher frequency. However, as the clock frequencyincreases, electromagnetic emission (EMI) increases due to an increasedpeak amplitude. As a result, EMI limits clock frequency improvements inthe related art.

[0005] A related art technique known as spread spectrum clocking (SSC)reduces EMI and allows for an increased clock frequency by modulatingthe clock frequency along a modulation profile having a predeterminedfrequency. Because amplitude is reduced by the frequency modulation, EMIcan be reduced while allowing an increase in the clock frequency. FIG. 1illustrates a non-modulated spectral energy distribution 3 compared tothe related art SSC frequency-modulated spectral energy distribution 1.A magnitude Δ of EMI reduction is determined by a modulation amount δand a shape of the SSC spectral energy distribution 1.

[0006]FIG. 2 illustrates a related art modulation profile 9 used withthe SSC technique. An SSC clock is modulated between a nominal frequency5 of the constant-frequency clock f_(nom), and a down-spreadingfrequency (1−δ) f_(nom) 7, where δ represents a spreading magnitude as apercentage of the nominal frequency f_(nom) 5. The modulation profile 9determines the shape of the SSC spectral energy distribution 1.

[0007]FIG. 3 illustrates a related art computer system that applies therelated art SSC technique. In a motherboard 15, an SSC generator 11receives an unmodulated clock input signal and generates afrequency-modulated clock signal in a first phase-locked loop (PLL) 13.The frequency-modulated clock signal is transmitted to a centralprocessing unit (CPU) 17 and a peripheral board 19.

[0008]FIG. 4 illustrates a block diagram of the SSC generator 11. Afirst divider 49 receives the unmodulated clock input signal andgenerates an output received by the first PLL 13. In the first PLL 13, afirst phase detector 35 receives an output signal of the first divider49 and an input signal from a feedback divider 43 to generate an outputsignal that provides a measurement of a phase difference between theunmodulated clock input signal and the frequency-modulated signal. Afirst charge pump 37 receives the output signal of the first phasedetector 35. The first charge pump 37 then generates charges in responseto the output signal of the first phase detector 35. When a first loopfilter 39 receives the charges from the first charge pump 37, the firstloop filter 39 produces a DC voltage output. The DC voltage output ofthe first loop filter 39 is received by a first voltage controlledoscillator (VCO) 41. The first VCO 41 generates an output signal to apost divider 45 and the feedback divider 43. The post divider 45 thengenerates the frequency-modulated clock signal that is transmitted tothe CPU 17 and the peripheral board 19, and the feedback divider 43generates a reference signal for the first phase detector 35.

[0009] As shown in FIG. 3, the peripheral board 19 further processes thefrequency-modulated clock signal in a zero-delay clock buffer 21 togenerate an output clock signal for a peripheral device 23 (e.g., SDRAM,accelerated graphics port, etc.). The zero-delay clock buffer 21includes a second PLL 25 having a second phase detector and a frequencydetector 27, a second charge pump 29, a second loop filter 31, and asecond voltage-controlled oscillator (VCO) 33.

[0010] However, the related art SSC technique has various disadvantages.For example, a jitter problem occurs due to a difference in periodbetween a maximum frequency and a minimum frequency. As the input clocksignal migrates from the non-modulated frequency over the modulationperiod, a change in period size occurs over clock cycles during amodulation event.

[0011] A skew problem also exists in the related art SSC technique dueto a period difference between the frequency-modulated clock signal andthe output clock signal. Because the output clock cannot be updatedinstantaneously, a period difference between the frequency-modulatedclock signal from the motherboard 15 and the output clock signal to theperipheral device 23 develops. The cumulative effect of the perioddifference results in a significant phase error known as skew.

[0012] The skew and jitter of the related art SSC technique can bereduced by maximizing a bandwidth of the feedback loop in the second PLL25 and minimizing a phase angle of an input-to-output transfer functionof the modulation frequency. FIGS. 5 and 6 illustrate a relationshipbetween increased feedback loop bandwidth, decreased phase angle, anddecreased skew. However, even the related art SSC technique havingoptimized feedback loop bandwidth and phase angle still has the jitterand skew errors as discussed in Zhang, Michael T., Notes on SSC and ItsTiming Impacts, Rev. 1.0, February 1998, pp. 1-8, which is incorporatedby reference. Thus, the jitter and skew problems limit the clockfrequency improvements that can be achieved by the related art SSCtechnique.

[0013] The above references are incorporated by reference herein whereappropriate for appropriate teachings of additional or alternativedetails, features and/or technical background.

SUMMARY OF THE INVENTION

[0014] An object of the invention is to solve at least the related artproblems and disadvantages, and to provide at least the advantagesdescribed hereinafter.

[0015] An object of the present invention is to provide an improvedzero-delay buffer circuit and a method therefor.

[0016] Another object of the present invention is to improve theefficiency.

[0017] A further object of the invention is to minimize a reduceselectromagnetic emission (EMI).

[0018] An object of the present invention is to also minimize thejitter.

[0019] Another object of the present invention is to minimize a skewerror.

[0020] Still another object of the present invention is to minimize adelay for clock skew elimination.

[0021] It is another object of the present invention to provide a phasedetector that eliminates a phase ambiguity problem.

[0022] A zero-delay buffer circuit for generating an output clock signalhaving a reduced EMI includes a spread spectrum clock (SSC) generatorcircuit that receives an input clock signal and generates a modulatedfrequency clock signal, and a zero-delay buffer circuit that receivesand buffers said modulated frequency clock signal to generate an outputclock signal, the zero-delay buffer circuit aligning a phase of themodulated frequency clock signal and the output clock signal such thatthere is no phase difference between the output clock signal and themodulated frequency clock signal.

[0023] A delay-locked loop circuit embodying the present inventionfurther includes a phase detector that receives a modulated frequencyclock signal, measures a phase difference between the modulated clockfrequency signal and the output clock signal, and generates phasedetector outputs; a charge pump circuit coupled to the phase detectordevice, wherein the charge pump circuit receives the phase detectoroutputs and generates charges; a loop filter circuit coupled to thecharge pump, wherein the loop filter circuit receives the charges andgenerates a DC voltage output; and a voltage controlled delay chain(VCDC) circuit coupled to the loop filter and the phase detector,wherein the VCDC circuit aligns phases of the modulated frequency clocksignal and the output clock signal.

[0024] A phase detection device embodying the present invention includesa first phase detector circuit that receives a modulated frequency clocksignal and generates first and second pulse signals, wherein the firstand second pulse signals measure on of a rising edge and a falling edgeof the modulated frequency clock signal and the output clock signal,respectively; a second phase detector circuit that receives themodulated frequency clock signal and generates third and fourth pulsesignals, wherein the third and fourth pulse signals measure one of therising edge and the falling edge of the modulated frequency clock signaland the output clock signal, respectively; and a signal divider circuitto alternatively operate the first and second phase detector circuit,memory states of the first phase detector circuit and the second phasedetector circuit are periodically reset.

[0025] A method embodying the present invention includes the steps ofgenerating a modulated frequency clock signal based on spread spectrummodulation having an amplitude less than an amplitude the input clocksignal; and aligning a phase of the modulated frequency clock signalwith the output clock signal to eliminate phase differences between theoutput clock signal and the modulated frequency clock signal.

[0026] Additional advantages, objects, and features of the inventionwill be set forth in part in the description which follows and in partwill become apparent to those having ordinary skill in the art uponexamination of the following or may be learned from practice of theinvention. The objects and advantages of the invention may be realizedand attained as particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The invention will be described in detail with reference to thefollowing drawings in which like reference numerals refer to likeelements wherein:

[0028]FIG. 1 illustrates a spectral energy distribution curve for afundamental harmonic of related art spread spectrum clocking (SSC) andnon-SSC clocks;

[0029]FIG. 2 illustrates a related art SSC modulation profile;

[0030]FIG. 3 illustrates a block diagram of the related art SSC systemarchitecture;

[0031]FIG. 4 illustrates a block diagram of the related art SSCgenerator having a phase-locked loop (PLL) circuit;

[0032]FIGS. 5 and 6 illustrate a relationship between feedback loopbandwidth, phase angle and skew for the related art SSC technique;

[0033]FIGS. 7a and 7 b illustrate a phase ambiguity problem of therelated art phase detector;

[0034]FIG. 8 illustrates a block diagram of a clock recovery circuitaccording to a preferred embodiment of the present invention;

[0035]FIG. 9 illustrates a block diagram of a delay-locked loop (DLL)circuit according to a preferred embodiment of the present invention;

[0036]FIG. 10 illustrates an operation of the DLL circuit according tothe preferred embodiment of the present invention;

[0037]FIGS. 11a and 11 b illustrate a time-to-digital converter (TDC)according to a preferred embodiment of the present invention;

[0038]FIG. 12 illustrates an operation of the TDC according thepreferred embodiment of the present invention;

[0039]FIG. 13 illustrates a block diagram of the DLL circuit accordingto another preferred embodiment of the present invention;

[0040]FIG. 14 illustrates an operation of the DLL circuit according toanother preferred embodiment of the present invention;

[0041]FIG. 15 illustrates a block diagram of the coarse delay linecircuit according to another preferred embodiment of the presentinvention;

[0042]FIG. 16 illustrates a block diagram of the controller circuit witha lock detector circuit according to another preferred embodiment of thepresent invention;

[0043]FIG. 17 illustrates a coarse tuning operation according to anotherpreferred embodiment of the present invention;

[0044]FIG. 18 illustrates a block diagram of a fine delay line circuitaccording to another preferred embodiment of the present invention;

[0045]FIG. 19 illustrates a phase detector according to the preferrz,999 e present invention; and

[0046]FIG. 20 illustrates an operation of the phase detector acco z,999d embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0047]FIG. 8 illustrates a block diagram of a spread spectrum clocking(SSC) clock system circuit according to a preferred embodiment of thepresent invention. A motherboard 83, a SSC generator 73, a PLL circuit81 and a CPU 77 are included. A peripheral board 75 includes azero-delay clock buffer circuit 68 having a delay-locked loop (DLL)circuit 69. The zero-delay clock buffer circuit 68 receives afrequency-modulated clock signal from the SSC generator 73 and outputsan output clock signal to a peripheral device (e.g., SDRAM, acceleratedgraphics port, etc.) 76. The DLL circuit 69 includes a phase detector71, a charge pump 72, a loop filter 73, and a voltage controlleddelay-chain (VDC) circuit 74.

[0048]FIG. 9 illustrates a block diagram of the DLL circuit 69 accordingto the preferred embodiment of the present invention. The DLL circuit 69includes a first time-to-digital converter (TDC) 85 coupled to a firstregister 87, and a second TDC 89 coupled to a second register 91. Thefirst and second registers 87, 91 are coupled to a controller 93, whichis coupled to a first coarse delay line circuit 95 and a first finedelay line circuit 97. The phase detector 71 is coupled to the chargepump 72 and the loop filter 73, and is also coupled to the first finedelay line circuit 97. The first fine delay line circuit 97 is alsocoupled to a clock buffer 99, which is coupled to the second TDC 89 andthe peripheral device 76.

[0049] In a preferred method embodying the present invention, the phasedetector 71 receives the frequency-modulated clock signal received fromthe SSC generator 73. The phase detector 71 then detects a phasedifference between the modulated frequency clock signal and the outputclock signal, and outputs a pulse signal to the charge pump 72. Thecharge pump 72 creates a charge based on the pulse signal from the phasedetector 71, and outputs a signal to the loop filter 73. The loop filter73 then outputs a voltage signal to the VCDC circuit 74, where the phasedifference detected by the phase detector 71 is eliminated. The VCDCcircuit 74 then produces an output signal that is transmitted to afeedback loop and a peripheral device 76.

[0050] In the method embodying the preferred embodiment of the presentinvention, the VCDC circuit 74 operates as follows. The first TDC 85receives and measures a period of the modulated frequency clock signaland converts the measured period into a first digital output signal. Thefirst register 87 receives and stores the digital output of the firstTDC 85. The second TDC receives an output of the clock buffer circuit99, and measures a total delay time of the first coarse delay linecircuit 95 and the first fine delay line circuit 97. The total delaytime is converted into a second digital output signal that is receivedand stored in the second register 91. The controller 93 receives thefirst and second digital output signals from the first and secondregisters 87, 91, and generates a control signal that is transmitted tothe first coarse delay line circuit 95.

[0051]FIG. 10 illustrates an operation of the DLL circuit 69 accordingto the preferred embodiment of the present invention. The first coarsedelay line circuit 95 delays the output clock signal based on thecontrol signal and transmits an output signal to the first fine delayline circuit 97. The first fine delay line circuit 97 receives an outputof the phase detector 71 and finely tunes the delay by aligning risingedges of the modulated frequency clock signal and the output clocksignal. In alternative embodiments of the present invention, fallingedges of the modulated frequency clock signal and the output clocksignal may be used for alignment.

[0052]FIGS. 11a and 11 b illustrate a TDC according to the preferredembodiment of the present invention. As shown in FIG. 13a, the TDCincludes a tapped delay line 101 having a plurality of taps, a pluralityof samplers 103, and a multiplexer 105. As shown in FIG. 13b, each ofthe taps 101 a includes a buffer 107 a that receives an input signal andgenerates an output signal transmitted to a subsequent tap 101 b and acorresponding flip flop gate 109 a that serves as the sampler 103. Theflip flop gate 109 a also receives the input signal, and generates anoutput sample signal. Each of the delay taps 101 a are coupled in seriesto a subsequent delay tap 101 b, and a last delay tap is coupled to themultiplexer 105. Similarly, the output sample signals are coupled to themultiplexer 105. The multiplexer then produces a digital output signal.

[0053]FIG. 12 illustrates an operation of the TDCs according to thepreferred embodiment of the present invention. A duration of an inputsignal is measured by calculating the number of delay taps in the inputsignal. In the preferred embodiment of the present invention, the inputsignal of the first TDC is the modulated frequency signal, and the inputsignal of the second TDC is the output clock signal. As each of thedelay taps produces a delayed version of the input signal, correspondingdelayed edges are produced at each tap of the delay line. Thus, the Dflip-flop gate 109 coupled to the delay tap 101 samples the data. Whenthe delay time is less than the duration of the input signal, the valueof the sampler output is set to “1.” In FIG. 14, the delay time is lessthan the input signal for an interval of four delay taps. Thus, thesampler output is set to “1” until T[5], when the sampler output changesto “0.” The sampler output signal produces a time value that isconverted to a digital value by the multiplexer 105. Accordingly, thetime value is then stored in the registers 87, 91.

[0054]FIG. 13 illustrates the DLL circuit according to another preferredembodiment of the present invention, wherein the first and second TDCs85, 89 have been replaced by a delayed pulse generator 27 and a seconddelay circuit 29, respectively. The second delay circuit 29 includes asecond coarse delay line circuit 31, a second fine delay line circuit32, and a dummy clock buffer 33 that are substantially similar to afirst delay circuit 30 including the first coarse delay line circuit 95,the first fine delay line circuit 97, and the clock buffer circuit 99.Further, the second delay circuit 29 and the first delay circuit 30share common control nodes in the DLL circuit 25. The dummy clock buffer33 preferably has substantially the same delay as the clock buffercircuit 99. Thus, a nominal delay of the second delay circuit 29approaches the delay between the frequency modulated clock signal iCLKto the output clock signal oCLK.

[0055]FIG. 14 illustrates an operation of the DLL circuit according toanother preferred embodiment of the present invention. The input to thedelayed pulse generator 27 is represented by id_CLK, while IDIV_CLK anddiv_CLK[i] represent first and second outputs, respectively, of thedelayed pulse generator 27 coupled to the second delay circuit 29 wherei equals a number of second output signals. Dummy delay elements 26 a,26 b match a delay of the first delay circuit 29 output oREP_CLK. Eachoutput div_CLK[i] of the delayed pulse generator 27 to the controller 93is aligned with a rising edge of the delayed frequency modulated clocksignal id_CLK. Additional delay elements 137 a, 137 b, 137 c, 137 d arecoupled in series to delay an output of the dummy clock buffer 33.Preferably, two delay elements 137 a, 137 b are counterparts to thedummy delay elements 26 a, 26 b to output oREP_CLK.

[0056]FIG. 15 illustrates a block diagram of the second coarse delayline circuit 31. A N:1 multiplexer 63 selects a tap, for example tap 61,from a plurality of taps, and the selected tap 61 is input to the secondfine delay line circuit 32. The tap selection is controlled by an UPcounter coupled to the multiplexer 63. The UP counter moves the selectedtap 61 to a direction of increasing delay time during the coarse tuningoperation, and initialized to have a minimum value at the start of thecoarse tuning operation. Thus, it is possible to achieve phase lock withonly the UP counter, and an UP/DOWN counter is not required. As aresult, jitter can be reduced by engaging a smaller number or thesmallest number of taps 61 for phase locking.

[0057]FIG. 16 illustrates a block diagram of the controller 93 accordingto another preferred embodiment of the present invention. Each of aplurality of lock detectors 64 . . . 64 n includes first and second Dflip-flops 65 a, 65 b that receive first and second outputs of thesecond delay circuit 29 oREP1_CLK, oREP2_CLK that are compared to thefirst output div_CLK[1] of the delayed pulse generator 27. The number oflock detectors preferably equals the number of second output signalsdiv_CLK[i] transmitted from the delayed pulse generator 27 to thecontroller 93. The two delayed outputs oREP1_CLK, oREP2_CLK form asampling window that indicates that the coarse locking process has beencompleted. Because the coarse locking process locates a delayed outputoREP_CLK in the vicinity of the delayed frequency modulated clock signalid_CLK, the coarse locking process has been accomplished when thesampled values at each of the D flip-flops 65 a, 65 b differs from eachother.

[0058] An output of each of the D flip-flops 65 a, 65 b is input to aNOR gate 67, and an output of the NOR gate 67 forms an output of thelock detector 64 C_LOCK[1]. Each lock detector output C_LOCK[i] isoutput to a corresponding input node of a (N+1)-input AND gate 131,which is coupled to the UP counter 133. The UP counter 133 is disabledwhen one of the lock detector outputs C_LOCK[i] has a zero value, and avalue of the UP counter 133 increases when a low-to-high transition ofoSP_CLK increases a delay of the output of the second delay circuitoREP_CLK. The second delayed output of the second delay circuit 29oREP2_CLKis delayed to produce an output oSP_CLK that accounts for atiming margin required to operate the UP counter 133.

[0059] An initial delay time of the delayed output of the second delaycircuit 29 oREP_CLK should be less than the delay time of a last delayedpulse required to achieve coarse lock. Otherwise, coarse locking cannotbe achieved because no lock detector 64 output C_LOCK[i] equals zero.The delay time of the delayed output oREP_CLK of the second delaycircuit 29 should be less than half of the delay time of the delay pulsegenerator 27 output IDIV_CLK that is the input of the second delaycircuit 29. The actual number of delay pulses is determined by anoperating speed and a coarse estimation to the time from the frequencymodulated clock signal iCLK to the output clock signal oCLK.

[0060]FIG. 17 illustrates operations of the coarse tuning operation.Here, the lock window is between the first and second delayed pulsegenerator outputs div_CLK[1], div_CLK[2]. Because the lock detectorcircuit 64 outputs C_LOCK[i] equal 1, the second delay circuit 29 outputoREP_CLK is increased. After several comparison cycles, the div_CLK[2]is in the locking window, and the coarse tuning operation is stopped.

[0061]FIG. 18 illustrates a block diagram of the first fine delay linecircuit 97, according to another preferred embodiment of the presentinvention. After the coarse tuning operation has been completed for thefirst coarse delay line circuit 95, the phase detector 71 adjusts thedelay time of the first fine delay line circuit 71 to achieve a phaselock between the frequency modulated clock signal iCLK and the outputclock signal oCLK. The phase detector 71 produces UP and DOWN pulses,and a pulse width depends on the phase difference of those two signals.The charge pump circuit 72 and attached loop filter 73 convert the phasedifference into the control voltage. A fine delay line circuit output isthen transmitted to the clock buffer 99.

[0062] The loop filter 73 of the DLL circuit is usually of the firstorder, and thus the overall loop of the DLL circuit is also first order.As is known in the related art, the first order loop has no stabilityproblem and thus the loop band width of the DLL circuit can be made aslarge as necessary. Thus, jitter and skew can be minimized or eliminatedwhen the DLL circuit is used as a zero delay buffer in the SSCenvironment.

[0063] Further, a phase ambiguity problem exists when a related artphase detector is applied to the zero-delay clock buffer circuit 21illustrated in FIG. 8. FIG. 7 illustrates an operation of the relatedart phase detector circuit 27 a. The operation of the phase detectorcircuit 27 a is directly affected by a sequence of the rising edge of aninput clock signal ICLK and an output clock signal oCLK. As shown inFIG. 7a, the phase detector generates a first pulse signal UP indicatinga rising edge of the input clock signal ICLK, and a second pulse signalDOWN indicating a rising edge of the output clock signal oCLK, tocalculate the phase difference. When a pulse width of the first pulsesignal UP is generated first, phase tracking is performed in the wrongdirection. However, FIG. 7b shows that phase tracking is performed inthe correct direction when the second pulse signal DOWN is generatedfirst. Thus, an incorrect phase difference output may result in therelated art phase detector circuit.

[0064]FIG. 19 illustrates the phase detector 71 according to thepreferred embodiment of the present invention. The phase detector 71includes a first phase detector circuit and a second phase detectorcircuit coupled to a signal divider circuit. The first and second phasedetector circuits can be in either a “reset” or an “operational” mode,and the mode of the first phase detector circuit must differ from themode of the second detector circuit, wherein the mode is determined byan output of the signal divider.

[0065] The first phase detector circuit includes first and second Dflip-flops 111,113, a first AND gate 121 and a first OR gate 125, andthe second phase detector circuit includes third and fourth D flip-flops115,117, a second AND gate 123 and a second OR gate 127. The signaldivider circuit includes a fifth D flip-flop 119 coupled to the firstphase detector circuit and the second phase detector circuit.

[0066] In the first phase detector circuit, the first D flip-flop 111 iscoupled to the modulated frequency clock signal ICLK and generates afirst pulse signal UP1, and the second D flip-flop 113 is coupled to theoutput clock signal oCLK and generates a second pulse signal DOWN1. Thefirst and second D flip-flops 111,113 are also commonly coupled to anoutput of the first OR gate 125 and a clear signal “1”. The first andsecond pulse signals UP1, DOWN1 are also input signals to the first ANDgate 121, and the first AND gate 121 generates an output signal receivedby a first input of the first OR gate 125.

[0067] In the second phase detector circuit, the third D flip-flop 115is coupled to the modulated frequency clock signal ICLK and generates athird pulse signal UP2, and the fourth D flip-flop 117 is coupled to theoutput clock signal OCLK and generates a fourth pulse signal DOWN2. Thethird and fourth D flip-flops 115,117 are also commonly coupled to anoutput of the second OR gate 127 and a clear signal “1”. The third andfourth pulse signals UP2, DOWN2 are also input signals to the second ANDgate 123, and the second AND gate 123 generates an output signalreceived by a first input of the second OR gate 127.

[0068] To set the mode of the first and second phase detector circuits,the fifth D flip-flop 119 is coupled to an inverted signal of themodulated frequency clock signal ICLK as a signal divider circuit. Thefifth D flip-flop 119 generates a first divider output signal divQ andan opposite second divider output signal divQB. A second input of thefirst OR gate 125 receives the first divider output signal divQ of thefifth D flip-flop 119, to determine if the first phase detector circuitis in the “reset” mode or the “operational” mode, and a second input ofthe second OR gate 127 receives the second divider output signal divQBof the fifth D flip-flop 119 to determine if the second phase detectorcircuit is in the “reset” mode or the “operational” mode.

[0069]FIG. 20 illustrates an operation of the phase detector 71according to the method embodying the present invention. When the firstdivider output signal divQ of the fifth D flip-flop 119 is set to “1,”the second divider output signal divQB of the fifth D flip-flop 119 isset to “0”. Correspondingly, the first phase detector circuit is in the“reset” mode and the second phase detector circuit is in the“operational” mode, and the first and second pulse signals UP1, DOWN1are set to “0” at a first time t₁. The second phase detector circuitgenerates the third pulse signal UP2 when the modulated frequency clocksignal value of “1” is detected, and generates the fourth pulse signalDOWN2 when the output clock signal value of “1” is detected. Thus, thecharge pump 72 generates the output signal based on the input valuesgenerated by the phase detector 71. When the first and second divideroutput signals div Q, div QB are reversed at a second time t₂, the firstphase detector circuit is in the “operational” mode and the second phasedetector circuit is in the “reset” mode.

[0070] The improved clock recovery circuit and method therefor embodyingthe present invention has various advantages. The zero-delay buffercircuit using DLL has inherently low jitter and low skew compared withthe related art zero-delay buffer using PLL.

[0071] Further, because the signal divider of the phase detectorperiodically resets the first and second phase detection circuits toclear their memories, phase tracking is performed in the correctdirection. Thus, the related art problem of phase ambiguity iseliminated.

[0072] The foregoing embodiments and advantages are merely exemplary andare not to be construed as limiting the present invention. The presentteaching can be readily applied to other types of apparatuses. Thedescription of the present invention is intended to be illustrative, andnot to limit the scope of the claims. Many alternatives, modifications,and variations will be apparent to those skilled in the art. In theclaims, means-plus-function clauses are intended to cover the structuresdescribed herein as performing the recited function and not onlystructural equivalents but also equivalent structures.

What is claimed is:
 1. A zero-delay buffer circuit in a spread spectrumclocking (SSC) system for generating an output clock signal having areduced electromagnetic emission (EMI), comprising: a SSC generatorcircuit that receives an input clock signal and generates a modulatedfrequency clock signal; and a zero-delay buffer circuit that receivesand buffers said modulated frequency clock signal to generate an outputclock signal, the zero-delay buffer circuit aligning a phase of themodulated frequency clock signal and the output clock signal such thatthere is no phase difference between the output clock signal and themodulated frequency clock signal.
 2. The zero-delay buffer circuit ofclaim 1, wherein the zero-delay buffer circuit is a delay-locked loop(DLL) circuit, comprising: a phase detector device that receives themodulated frequency clock signal and the output clock signal to generatephase detector output signals indicative of a phase difference betweenthe modulated frequency clock signal and the output clock signal; acharge pump circuit coupled to the phase detector device for receivingthe phase detector output signals and generating charge pump signals; aloop filter circuit receiving the charge pump signals; and a voltagecontrolled delay chain (VCDC) circuit coupled to the loop filter and thephase detector, wherein the VCDC circuit aligns phases of the modulatedfrequency clock signal and the output clock signal.
 3. The zero-delaybuffer circuit of claim 2, wherein the phase detector device furthercomprises: a first phase detector circuit that receives the modulatedfrequency clock signal and generates first and second pulse signalsindicative of one of a rising edge and a falling edge of the modulatedfrequency clock signal and the output clock signal, respectively; asecond phase detector circuit that receives the modulated frequencyclock signal and generates third and fourth pulse signals indicative ofone of the rising edge and the falling edge of the modulated frequencyclock signal and the output clock signal, respectively; and a signaldivider circuit to alternatively operate the first and second phasedetector circuit in one of an operational mode and a reset mode.
 4. Thezero-delay buffer circuit of claim 3, wherein the first phase detectorcomprises: first and second logic gates, an output of the first logicgate being coupled to a first input of the second logic gate and asecond input of the second logic gate being coupled to a first output ofthe signal divider circuit, a first flip-flop coupled to a first inputof the first logic gate, a constant signal, and an output of the secondlogic gate and responsive to the modulated frequency clock signal, asecond flip flop coupled to a second input of the first logic gate, theconstant signal, and the output of the second logic gate and responsiveto the output clock signal; the second phase detector circuit comprises:third and fourth logic gates, an output of the third logic gate beingcoupled to a first input of the fourth logic gate and a second input ofthe fourth logic gate being coupled to a second output of the signaldivider circuit, a third flip flop coupled to a first input of a thirdlogic gate, the constant signal, and an output of the fourth logic gateand responsive to the modulated frequency clock signal, a fourth flipflop coupled to a second input of the third logic gate, the constantsignal, and the output of the fourth logic gate, and responsive to theoutput clock signal, and the signal divider circuit comprises a fifthflip-flop coupled to the modulated frequency clock signal and inputs ofthe second and fourth logic gates.
 5. The zero-delay buffer circuit ofclaim 4, wherein the first and third logic gates are AND logic gates,and the second and fourth logic gates are OR logic gates.
 6. The zerodelay buffer circuit of claim 2, wherein the VCDC circuit furthercomprises: a delayed pulse generator that receives and delays themodulated frequency clock signal to generate a delayed modulatedfrequency clock signal, and generates a first output signal and a secondoutput signal based on the delayed modulated frequency clock signal; afirst delay line circuit that receives the first output signal, acontrol signal and a second delay line circuit output signal indicativeof a delay between the output clock signal and the modulated frequencyclock signal, and generates a plurality of third output signalscontrolled by the control signal, wherein the third output signals areindicative of the delay between the output clock signal and the delayedmodulated frequency clock signal; a controller circuit that receives thesecond output signal and the third output signals and generates thecontrol signal, wherein the control signal is indicative of a delaybetween the second output signal and the third output signals; and asecond delay line circuit that receives the control signal, the modifiedfrequency clock signal and the phase detector output signal to generatethe output clock signal and the second delay line circuit output signal.7. The zero buffer delay circuit of claim 6, wherein the first delayline circuit further comprises: a first coarse delay line circuit thatreceives the first output signal and the control signal and generates afirst coarse delay line circuit output signal; a first fine delay linecircuit that receives the first coarse delay line circuit output signaland the second delay line circuit output signal and generates a firstfine delay line circuit output signal; and a first buffer circuit thatreceives the first fine delay line circuit output signal and generatesthe third output signals; and wherein the second delay line circuitcomprises: a second coarse delay line circuit that receives themodulated frequency output signal and the control signal and generates asecond coarse delay line circuit output signal indicative of a delaybetween the modulated frequency clock signal and the output clocksignal, a second fine delay line circuit that receives the second coarsedelay line circuit output signal and the phase detector output signaland generates the second delay line circuit output signal, and a secondbuffer circuit that receives the second delay line circuit output signaland generates the output clock signal.
 8. The zero delay buffer circuitof claim 7, wherein the first coarse delay line circuit comprises: acoarse delay line having plurality of coarse delay cells that receiveand delay the delayed modulated frequency clock signal and generate acorresponding plurality of coarse delay cell output signals; and amultiplexer that receives the plurality of coarse delay cell outputsignals and the control signal to generate the first coarse delay linecircuit output signal.
 9. The zero delay buffer circuit of claim 7,wherein the second fine delay line circuit comprises a fine delay linehaving plurality of fine delay line cells that receive the coarse delayline circuit output signal and the phase detector output signal, delaythe second coarse delay line output signal based on the phase detectoroutput signal, and generate the second delay line circuit output signal.10. The zero delay buffer circuit of claim 6, wherein the controllercircuit comprises: a plurality of lock detectors that receive the secondoutput signal and the third output signals and generate correspondinglock detector output signals; a logic circuit that receives the lockdetector output signals and a delayed third output signal and generatesa fourth output signal based on the lock detector output signals and thedelayed third output signal; and a counter that receives the fourthoutput signal and generates the control signal.
 11. The zero delaybuffer circuit of claim 10, wherein each of the lock detectorscomprises: a plurality of flip-flops that generate a plurality of fifthoutput signals, wherein each of the flip-flops receives the secondoutput signal and one of the third output signals and generates one ofthe plurality of fifth output signals; and a NOR logic gate thatreceives the fifth output signals and generates one of the correspondinglock detector output signals indicative of a delay between the secondoutput signal and the third output signals, wherein the logic circuit isan AND logic gate.
 12. A delay-locked loop (DLL) circuit, comprising: aphase detector device that receives a modulated frequency clock signaland an output clock signal to generate phase detector output signalsindicative of a phase difference between the modulated frequency clocksignal and the output clock signal; a charge pump circuit coupled to thephase detector device for receiving the phase detector output signalsand generating charge pump signals; a loop filter circuit receiving thecharge pump signals; and a voltage controlled delay chain (VCDC) circuitcoupled to the loop filter and the phase detector, wherein the VCDCcircuit aligns phases of the modulated frequency clock signal and theoutput clock signal.
 13. The DLL circuit of claim 12, comprising: adelayed pulse generator that receives and delays the modulated frequencyclock signal to generate a delayed modulated frequency clock signal, andgenerates a first output signal and a second output signal based on thedelayed modulated frequency clock signal; a first delay line circuitthat receives the first output signal, a control signal and a seconddelay line circuit output signal indicative of a delay between theoutput clock signal and the modulated frequency clock signal, andgenerates a plurality of third output signals controlled by the controlsignal, wherein the third output signals are indicative of the delaybetween the output clock signal and the delayed modulated frequencyclock signal; a controller circuit that receives the second outputsignal and the third output signals and generates the control signal,wherein the control signal is indicative of a delay between the secondoutput signal and the third output signals; and a second delay linecircuit that receives the control signal, the modified frequency clocksignal and the phase detector output signal to generate the output clocksignal and the second delay line circuit output signal.
 14. The DLLcircuit of claim 12, wherein the phase detection device comprises: afirst phase detector circuit that receives the modulated frequency clocksignal and generates first and second pulse signals indicative of one ofa rising edge and a falling edge of the modulated frequency clock signaland the output clock signal, respectively; a second phase detectorcircuit that receives the modulated frequency clock signal and generatesthird and fourth pulse signals indicative of one of the rising edge andthe falling edge of the modulated frequency clock signal and the outputclock signal, respectively; and a signal divider circuit toalternatively operate the first and second phase detector circuit in oneof an operational mode and a reset mode.
 15. The DLL circuit of claim14, wherein the first phase detector circuit comprises: first and secondlogic gates, an output of the first logic gate being coupled to a firstinput of the second logic gate and a second input of the second logicgate being coupled to a first output of the signal divider circuit, afirst flip-flop coupled to a first input of the first logic gate, aconstant signal, and an output of the second logic gate and responsiveto the modulated frequency clock signal, a second flip flop coupled to asecond input of the first logic gate, the constant signal, and theoutput of the second logic gate and responsive to the output clocksignal; the second phase detector circuit comprises: third and fourthlogic gates, an output of the third logic gate being coupled to a firstinput of the fourth logic gate and a second input of the fourth logicgate being coupled to a second output of the signal divider circuit, athird flip flop coupled to a first input of a third logic gate, theconstant signal, and an output of the fourth logic gate and responsiveto the modulated frequency clock signal, a fourth flip flop coupled to asecond input of the third logic gate, the constant signal, and theoutput of the fourth logic gate, and responsive to the output clocksignal, and the signal divider circuit comprises a fifth flip-flopcoupled to the modulated frequency clock signal and inputs of the secondand fourth logic gates.
 16. The DLL circuit of claim 15, wherein thefirst and third logic gates are AND logic gates, and the second andfourth logic gates are OR logic gates.
 17. A method of generating anoutput clock signal having a reduced electromagnetic emission (EMI),comprising the steps of: generating a modulated frequency clock signalbased on spread spectrum modulation having an amplitude less than anamplitude of the input clock signal; and aligning a phase of themodulated frequency clock signal with the output clock signal toeliminate phase differences between the output clock signal and themodulated frequency clock signal.
 18. The method of claim 17, whereinthe aligning step comprises: measuring a period of the modulatedfrequency clock signal to generate a first delayed modulated frequencyclock signal; measuring a period of the output clock signal; generatinga control signal indicative of a difference between the period of adigital signal that measures a time of the period of the first delayedmodulated frequency clock signal, and a signal that measures a time ofthe period of the output clock signal; delaying a phase of the modulatedfrequency clock signal based on the control signal to generate a seconddelayed modulated frequency clock signal; detecting a phase differencebetween the modulated frequency clock signal and the output clocksignal; and aligning edges of the second delayed modulated frequencyclock signal based on the phase difference.
 19. The method of claim 17,wherein the step of detecting a phase difference comprises: receivingthe modulated frequency clock signal and the output clock signal;detecting a difference between the modulated frequency clock signal andthe output clock signal; detecting one of a rising edge and a fallingedge of the modulated frequency clock signal and the output clocksignal; generating a first phase output when one of the rising edge andthe falling edge of the modulated frequency clock signal is detected,and a second phase output signal when one of the rising edge and thefalling edge of the output clock signal is detected; and generating adivided signal that alternates a plurality of phased detector circuits.20. A phase detection device, comprising: a first phase detector circuitthat receives a modulated frequency clock signal and generates first andsecond pulse signals indicative of one of a rising edge and a fallingedge of the modulated frequency clock signal and an output clock signal,respectively; a second phase detector circuit that receives themodulated frequency clock signal and generates third and fourth pulsesignals indicative of one of the rising edge and the falling edge of themodulated frequency clock signal and the output clock signal,respectively; and a signal divider circuit to alternatively operate thefirst and second phase detector circuit in one of an operational modeand a reset mode.
 21. The phase detection device of claim 20, whereinthe first phase detector circuit comprises: first and second logicgates, an output of the first logic gate being coupled to a first inputof the second logic gate and a second input of the second logic gatebeing coupled to a first output of the signal divider circuit, a firstflip-flop coupled to a first input of the first logic gate, a constantsignal, and an output of the second logic gate and responsive to themodulated frequency clock signal, a second flip flop coupled to a secondinput of the first logic gate, the constant signal, and the output ofthe second logic gate and responsive to the output clock signal; thesecond phase detector circuit comprises: third and fourth logic gates,an output of the third logic gate being coupled to a first input of thefourth logic gate and a second input of the fourth logic gate beingcoupled to a second output of the signal divider circuit, a third flipflop coupled to a first input of a third logic gate, the constantsignal, and an output of the fourth logic gate and responsive to themodulated frequency clock signal, a fourth flip flop coupled to a secondinput of the third logic gate, the constant signal, and the output ofthe fourth logic gate, and responsive to the output clock signal, andthe signal divider circuit comprises a fifth flip-flop coupled to themodulated frequency clock signal and inputs of the second and fourthlogic gates.
 22. The phase detection device of claim 21, wherein thefirst gate and third logic gates are AND gates, and the second andfourth logic gates are OR gates.
 23. The phase detection device of claim20, wherein the signal divider circuit alternates modes of the firstphase detector circuit and the second phase detector circuit based onoutputs of the fifth flip-flop.